The present invention relates to a bias circuit and a method of fabricating a bipolar integrated circuit in which elements of the bias circuit are integrated.
Recently, a field effect transistor formed from GaAs with small power consumption (MESFET) is widely used as a transistor of a transmitting power amplifier used in mobile communication equipment such as a portable telephone. A negative power source is generally used for bias for a gate electrode of a MESFET. Accordingly, in using a MESFET in a transmitting power amplifier, two power sources, namely, a positive power source and a negative power source, are required. This is a disadvantage to downsizing of the amplifier, and hence, a transistor operated by a positive power source alone is earnestly desired.
Furthermore, in recent communication systems such as CDMA (code division multi-channel access), an output current of a transmitting power amplifier is required to have small distortion (namely, to be linear). As a transistor meeting these requirements, a heterojunction bipolar transistor (HBT) including the emitter formed from a semiconductor having a larger band gap than a semiconductor forming the base is practically used.
In a conventional power amplifier using HBTs, a bias circuit is generally constructed on the same chip for supplying a current necessary for the base of an HBT used as a power transistor. An HBT has, however, a characteristic that the on state voltage decreases as the temperature increases as is shown in FIG. 10 (which characteristic is hereinafter referred to as the temperature characteristic of an HBT). Therefore, when a given voltage is applied between the base and the emitter, a collector current (hereinafter referred to as the idle current) of the HBT is largely increased as the temperature increases. Accordingly, the bias circuit is required to reduce change with temperature of the idle current of the HBT serving as the power transistor.
A bias circuit for overcoming the problem will now be described with reference to FIG. 11, which shows a bias circuit 100 used in a conventional power amplifier.
The base terminal of a bipolar transistor Tro101 serving as a power transistor is connected through a resistor R103 of 4 xcexa9 to a bipolar transistor Tr102 so as to compose an emitter-follower circuit. Also, the base terminal of the transistor Tr102 is grounded through transistors Tr103 and Tr104 in each of which the base and the collector are short-circuited. The transistors Tr103 and Tr104 are PN diodes having the same on state voltage as the transistors Tr101 and Tr102. When the temperature is increased in this circuit, the idle current C of the transistor Tr101, that is, the HBT, is increased owing to the temperature characteristic. On the other hand, a current flowing through the transistors Tr103 and Tr104 is also increased owing to the same temperature characteristic. Accordingly, a current flowing through a resistor R101 connected to the transistors Tr103 and Tr104 in series is increased. Since the resistance of the resistor R101 is constant (530 xcexa9), a voltage applied to the resistor R101 is increased as the current increases. In other words, a potential at a point P5 of FIG. 11 is lowered. Accordingly, the base potential of the transistor Tr102 connected to the resistor R101 is lowered. As a result, the emitter current of the transistor Tr102 is decreased, so as to lower the base potential of the power transistor Tr101. In this manner, the idle current C of the power transistor Tr101 can be suppressed from increasing.
The bias circuit too of FIG. 11 thus suppresses the idle current C of the power transistor Tr101 from increasing in accordance with the temperature increase.
In the conventional bias circuit 100, however, the suppression of the change of the idle current is disadvantageously insufficient.
The present invention was devised to overcome the aforementioned disadvantage, and an object is providing a bias circuit in which change with temperature of an idle current of a power transistor is suppressed and a method of fabricating a semiconductor device including the bias circuit.
The bias circuit of this invention comprises a first bipolar transistor having an emitter, a base and a collector; and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is disposed for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.
In a bipolar transistor, the collector current is changed in accordance with temperature change when a given voltage is applied between the base and the emitter. Since the Schottky diode is provided so as to supply a base potential for suppressing the change, a substantially constant collector current can be obtained regardless of the temperature change.
The bias circuit preferably further comprises a second bipolar transistor having an emitter, a base and a collector; a PN diode connected to the base of the second bipolar transistor; and two or more Schottky diodes connected to the base of the second bipolar transistor, and the emitter of the second bipolar transistor is preferably connected to the base of the first bipolar transistor, and the two or more Schottky diodes are preferably connected to the PN diode in series.
When the PN diode and the two or more Schottky diodes are connected to the base of the second bipolar transistor, a current flowing through the PN diode and the two or more Schottky diodes is increased as the temperature increases with a given voltage applied to the bias circuit, and hence, the base potential of the second bipolar transistor can be lowered. As a result, the emitter current of the second bipolar transistor is decreased, so as to lower the base potential of the first bipolar transistor. Accordingly, the collector current of the first bipolar transistor can be suppressed from increasing. When the temperature decreases, the collector current of the first bipolar transistor can be suppressed from decreasing in accordance with the temperature decrease through a mechanism completely reverse to that described above. In particular, a Schottky diode has a smaller on state voltage than a PN diode used in the conventional bias circuit. Also, the change with temperature of the on state voltage of the Schottky diode is substantially the same as change with temperature of the on state voltage of the PN diode. Accordingly, in the two or more serially connected Schottky diodes, the change of a current caused by changing the temperature under application of the same voltage as in the PN diode can be larger than in the PN diode. As a result, the base potential of the first bipolar transistor can be more largely changed so as to more sufficiently suppress the change of the collector current of the first bipolar transistor.
The bias circuit preferably further comprises a second bipolar. transistor having an emitter, a base and a collector; and three or more Schottky diodes connected to the base of the second bipolar transistor in series, and the emitter of the second bipolar transistor is preferably connected to the base of the first bipolar transistor.
In the three or more serially connected Schottky diodes, the change of a current caused by changing the temperature under application of the same voltage as in the PN diode can be larger than in the PN diode. Accordingly, the base potential of the first bipolar transistor can be more largely changed so as to more sufficiently suppress the change of the collector current of the first bipolar transistor.
The bias circuit preferably further comprises at least one Schottky diode connected to be branched from connection between the emitter of the second bipolar transistor and the base of the first bipolar transistor.
In the Schottky diode connected to be branched from the connection of the base of the first bipolar transistor, the change of a current caused by changing the temperature under application of the same voltage in a PN diode can be larger than in the PN diode. Accordingly, the base potential of the first bipolar transistor can be more largely changed so as to more sufficiently suppress the change of the collector current of the first bipolar transistor.
The first and second bipolar transistors can be heterojunction bipolar transistors.
The bias circuit preferably further comprises a second bipolar transistor having an emitter, a base and a collector; and one or more Schottky diodes connected to the base of the second bipolar transistor in series, and the collector of the second bipolar transistor is preferably connected to the base of the first bipolar transistor.
When the temperature is increased, the on state voltage of each of the one or more Schottky diodes serially connected to the base of the second bipolar transistor is decreased, and hence, the base potential of the second bipolar transistor is increased. As a result, the collector current of the second bipolar transistor is increased not only due to the temperature increase but also due to the increase of the base potential. When the collector current of the second bipolar transistor is increased, the base potential of the first bipolar transistor connected to the collector of the second bipolar transistor is lowered. Accordingly, the collector current of the first bipolar transistor can be suppressed from increasing in accordance with the temperature increase. When the temperature is decreased, the collector current of the first bipolar transistor can be suppressed from decreasing in accordance with the temperature decrease through a mechanism completely reverse to that described above.
The method of this invention of fabricating a semiconductor device including a bipolar transistor having an emitter, a base and a collector, a semiconductor region and a Schottky diode having a Schottky electrode in Schottky contact with the semiconductor region, comprises the steps of (a) forming an emitter electrode on a semiconductor substrate including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type deposited on the first semiconductor layer and a third semiconductor layer of the first conductivity type deposited on the second semiconductor layer; (b) forming an emitter layer and a base layer by patterning the third semiconductor layer and the second semiconductor layer by using an etching mask masking the emitter electrode and an area around the emitter electrode, and exposing a surface of the first semiconductor layer after forming the emitter layer and the base layer; (c) forming an isolation region for dividing the first semiconductor layer between a collector region and a Schottky diode region after the step (b); (d) exposing part of a surface of the base layer by patterning the emitter layer; and (e) forming a base electrode on the exposed surface of the base layer, and forming the Schottky electrode on the first semiconductor layer in the Schottky diode region.
According to this method, a semiconductor device including a bipolar transistor and a Schottky diode formed on the same substrate can be fabricated.
In the step (e), the base electrode and the Schottky electrode are preferably simultaneously formed.
Thus, there is no need to conduct additional procedures for forming a-new semiconductor layer and forming a Schottky electrode in order to add a Schottky diode to the semiconductor device. In other words, a semiconductor device including a Schottky diode formed on the same chip can be fabricated without increasing the number of procedures as compared with that of a method of fabricating a conventional semiconductor device including a bipolar transistor.
In the step (a), the semiconductor substrate can further include, below the first semiconductor layer, a fourth semiconductor layer having a higher concentration of an impurity of the first conductivity type than the first semiconductor layer, in the step (c), the isolation region can also divides the fourth semiconductor layer between the collector region and the Schottky diode region, and the method can further include, after the step (b), the steps of forming, in the first semiconductor layer, openings for exposing a surface of the fourth semiconductor layer in the collector region and in the Schottky diode region; and simultaneously forming a collector electrode and an ohmicelectrode on the fourth semiconductor layer within the openings.
The forbidden band with of a semiconductor used for forming the third semiconductor layer can be larger than that of a semiconductor used for forming the second semiconductor layer.